1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device, a test circuit of a semiconductor memory device, and/or a test method.
This application claims the priority of Korean Patent Application No. 2003-36745, filed on Jun. 9, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A memory cell test is one of the most important processes during manufacturing of a semiconductor memory device (e.g. a dynamic random access memory (DRAM) and a read only memory (ROM)). In the memory cell test, it is determined if the semiconductor memory device is working properly by confirming that data output from memory cells under test meets the expected test values. During a memory cell test, there is latency between reference data input into the tested memory device during a write operation and data reference data output from the memory device during a read operation. Latency is the processing time required for reading and writing data after inputting the reference data in the semiconductor memory device. Latency may be influenced by the process of reading and writing data, physical characteristics of signal lines, and circumstances under which the semiconductor memory device operates.
In the process of detecting an error by comparing the reference data and the data output from the tested memory device, a common starting point between the reference data and the output data should be set. Once the starting points of the reference data and the output data are respectively detected, a comparison of the data can occur. In order to do this, a circuit compensating latency between the reference data and the output data is needed.
Initially, a starting point of the reference data and output data should be determined. For the reference data, a starting signal can be directly produced when generating data outside of a device. Although the starting signal may be generated inside of the device, it can be easily detected since the starting signal is generated by a control signal which originates outside of the device. For the output data, an exact data starting point is not easily detected since the data is generated at the tested memory device. That is, it is very difficult to estimate a definite starting point of the output data value in advance because latency between memory devices varies. However, a value range of the starting point may be estimated based on typical results. The variation in latency may be influenced by on-chip variations, circumstances under which the semiconductor memory device operates, and connecting structures of the semiconductor memory device. Accordingly, an extra signal which is generated outside is used to indicate the starting point of output data in a related art method.
FIG. 1 is a drawing illustrating a related art latency processing method. The DATA SYNC SIGNAL is a signal indicating a start of the OUTPUT DATA. A system outside of the semiconductor memory device detects an error by recognizing the OUTPUT DATA as meaningful data when the DATA SYNC SIGNAL is changed from a first logic state to a second logic state, after inputting the REFERENCE DATA in the semiconductor memory device. The activation of the DATA SYNC SIGNAL, indicates a starting point of the OUTPUT DATA. An extra signal line is necessary (e.g. the DATA SYNC SIGNAL for informing the start of the OUTPUT DATA. Accordingly, the starting point of the OUTPUT DATA can be checked by using the extra signal line. Moreover, another method for detecting latency is by latching the OUTPUT DATA, as disclosed in Korean Patent No. 1997-62994. In this method, an extra circuit is necessary to synchronize the DATA SYNC SIGNAL outside of the semiconductor memory device, thereby complicating a system, causing a delay of signals, and increasing power consumption.